The Vai Logic ASIC design team consists of a team of highly skilled engineers with over 130 years of experience and over 35 patents. We offer multiple customer engagement models:

• Contract labor
• Our team members are available to integrate into your project team either on-site or remote.


• Complete, verified netlist or tapeout generation:
• Using your specifications, our team can develop the RTL code and synthesize the gate level netlist. The design will be verified through simulation and can be validated using an FPGA platform.
• Using your (or our) Netlist and your targeted foundry libraries, our team can complete the physical design of your IC.


• Verification, Validation, and Application
• Our team can assist you in any phase of verification and validation including. Creation and execution of RTL and Gate Level test benches, FPGA verification of Netlist, Custom PCB and SW design for final IC validation and customer application platform.

Early-to-Market (ETM) Design Philosophy

• Insure "first time right" designs for high volume production
• IC Development flow shown below:

For more information regarding ASIC Design Services from Vai Logic, please contact us at info@vaitechnology.com.